The present invention relates to phase locked loops. More particularly, the present invention relates to frequency-phase detectors for phase locked loops and methods for operating the same.
FIG. 1 is a circuit diagram illustrating a conventional phase locked loop (PLL). As shown in FIG. 1, the phase locked loop includes a frequency-phase detector (PFD) 110, a charge pump 120, a loop filter 130 and a voltage controlled oscillator (VCO) 140.
The frequency-phase detector 110 detects frequency differences and/or phase differences between an input signal Fin and an output signal Fout, and then sends to the charge pump 120 pump-up/down signals. The pump-up/down signals correspond to error signals based on detected frequency and/or phase differences.
The charge pump 120 provides an up current I1 or a down current I2 through a pump-up switch and a pump-down switch, respectively, in response to the pump-up signal and the pump-down signal, so as to charge or discharge capacitors in the loop filter 130. The voltage controlled oscillator 140 outputs the output signal Fout having frequency proportional to a voltage provided from the loop filter 130. The output signal Fout is fed back to the frequency/phase detector 110 to be compared with the input signal Fin.
Thus, as described above, the phase locked loop circuit of FIG. 1 may output the output signal Fout having a phase and a frequency that are controlled to track and match those of the input signal Fin, and, when the input and output match, the state of the phase locked loop circuit may be referred to as a lock state. Before the phase locked loop reaches the lock state, the phase difference between the two inputs Fin and Fout becomes progressively smaller. Accordingly, as the difference becomes very small, a width of the pump-up/down signals also becomes very narrow. As a result of this narrow signal width, the charge pump 120 may fail to respond to the up/down signals and may not charge or discharge the capacitors of the loop filter 130, despite the existence of a phase error, within a certain range of phase difference. Such a range of non-corrected error may be referred to as a dead zone. The dead zone may cause a static phase error and degrade a jitter characteristic of the phase lock loop.
To address such problems, a conventional PLL typically delays a reset signal(s) of the frequency-phase detector, which is reset when both the up signal and the down signal are activated. The dead zone may be reduced or even eliminated by delaying the reset signal(s) through a delay circuit for a selected time after both of the up/down signals are activated.
FIG. 2 is a circuit diagram illustrating a conventional frequency/phase detector having a reset signal generator. As shown in FIG. 2, a reset signal VRST is activated when both of the pump-up/down signals are activated. The reset signal VRST resets the frequency-phase detector 210 after a selected delay time provided by passing the reset signal VRST through a delay device 220.
As a result of the circuit of FIG. 2, although a phase difference between two inputs Fin and Fout of the frequency-phase detector 210 becomes very small, widths of the up/down signals may be maintained for a delay time of the delay device 220, and, thus, the dead zone may be decreased or even eliminated.
Various problems may be encountered with the circuit of FIG. 2. In particular, the delay time may vary depending upon manufacturing process variations for the circuit and it may be difficult to determine a suitable delay time because the delay time generally varies depending upon the manufacture process variations during actual circuit implementations. If the delay time is set too long, the current consumption generally increases in the lock state. If the delay time is set too short, the dead zone may not be effectively reduced/removed. As a result, a static phase error may occur and jitter characteristics of the phase lock loop may be degraded.
U.S. Pat. No. 6,566,923 “PHASE-FREQUENCY DETECTOR AND CHARGE PUMP WITH FEEDBACK” discloses a charge pump, which has two switches to be controlled simultaneously by signals to charge or to discharge the charge pump, respectively. Additionally, a circuit to provide a reset signal is disclosed, the circuit activating the reset signal only if both of the signals are in a flowing state. Therefore, this approach may more effectively reset the phase-frequency detector than the frequency-phase detector that provides a delayed reset signal through the delay device 220 as described with reference to FIG. 2.
The U.S. Pat. No. 6,566,923 provides signals picked up by a drain switch approach, from the two switches, which are coupled to each of two current sources. The drain switch approach may, however, cause a current spike due to a sudden voltage change between two terminals of each of the current sources. For the circuit of U.S. Pat. No. 6,566,923, when both of the two switches are in a closed state, a voltage between a source voltage level and ground level may be applied onto the current source, which may overburden the current source and increase current consumption. Furthermore, the reset signal may be generated before the charge pump provides sufficient up or down currents.